In data processing environments, buffering data has been a widely-used technique ever since the first data processors were constructed. For example, in an article by West, et al "A Digital Computer For A Scientific Application", Proceedings of the IRE, December 1948, pp. 1452-3, shows a buffering system of the alternating buffer type. A pair of buffer units are provided. While data is being read into a first buffer unit, data in a second buffer unit is being read out. These functions are alternated between the two buffer units such that an apparent wide-band flow of data goes through the buffer while using electronic circuits that operate at a speed slower than that would be required if the buffer units were not alternated.
A more common type of data buffering is the so-called first in, first out (FIFO) buffer characterized by a read-in counter and a read-out counter where the read-in counter indicates the memory address which is to next receive data while the read-out counter identifies the address of the register in the buffer containing data next to be read out. An example of such a buffer is shown in the IBM Technical Disclosure Bulletin, Vol. 15, No. 8, January 1973, in an article by L. B. Baumer, entitled "Read-Only Memory Controlled Buffering", on pp. 2495-6. Even with these types of buffering, the unit receiving the data must also provide buffering before the accumulated data can be processed; otherwise, data is processed by the receiver at the rate that the data is read out of the buffer.
One of the problems in a FIFO buffer is overrun and underrun such as set forth in U.S. Pat. No. 4,040,027, priority Netherlands, Apr. 25, 1975, as serial number 75/04901. This patent shows a FIFO buffer having a measuring device indicating the extent to which the buffer memory is filled or emptied. The measuring device then controls the data read in and data read out such that a predetermined filling of the buffer is maintained. U.S. Pat. No. 4,145,739, on the other hand, in column 16 and in FIGS. 17-19 shows a buffer control which does not output data until eleven bits have been inputted to the buffer. In other words, the buffer also serves as a data accumulator. U.S. Pat. No. 4,298,954 shows an alternating buffer system operating in a FIFO mode but which has a broader bandwidth in that alternation between the buffers is speeded up over that provided by earlier alternating buffers; that is, when a buffer is empty, alternation occurs even though the other buffer is not completely filled. In this manner, the alternation rate is determined by the buffer content as opposed to the slowest data rate, thereby enhancing data bandwidth.
Not only have electronic circuits been employed in controlling buffering data but also computer programs have been employed in buffering data, such as within the main memory of a processor. In such buffering, alternating buffering techniques have been used for inputting and outputting data from and to peripheral devices attached to the processor. In such a situation, a portion of main memory is allocated for the buffering function, and the programming controls the buffering operations. In newer computers, a programmed channel processor provides the buffering control. The techniques and logic employed in controlling such program-controlled buffering follows that of the earlier described hardware or electronic circuit controlled buffers. When this logic of control is employed in a programmed processor, the program controls for the buffer and the processing are logically independent, i.e., the buffer program control merely replaces electronic circuit controls. An example of such a control is shown in the IBM Technical Disclosure Bulletin, October 1971, Vol. 14, No. 5, in an article by J. L. Wescott, entitled "Buffer Management in a Multitasking Environment", on pp. 1404-1407. On page 1406, it is stated that the processor task receives full input buffers, i.e., the buffering within main memory occurs as if the buffering portion of the main memory were controlled as described for the electronic-circuit controlled buffers. A similar situation is disclosed in the IBM Technical Disclosure Bulletin, July 1973, Vol. 16, No. 2, pp. 658-661, in an article by M. E. Stump, entitled "First In-First Out Space Management". Again the logic of control separates the buffer management function from the data processing functions. As data rates increase, such separation tends to slow down the total data processing function within a programmed environment. Accordingly, it is desired to provide buffering controls that do not slow down the processing of data, allow a maximal overlap of processing and buffering functions and is achieved in a relatively simple manner.